latticeecp2 latticeecp2m

The realization of memory controller using the programmed gate array (FPGA) has the great advantage â€“ it makes possible to reduce a quantity of elements in construction, which is critically importantly for systems, developed taking in account hard constraints on the overall sizes. Furthermore, and now and then this consideration leaves to the foreground, designers obtain the additional flexibility of controller it can be added into the already existing project with the minimum modifications.

Well-known developer and producer OF FPGA, Lattice semiconductor declared about the release of controller synchronous dynamic memory with the arbitrary access (SDRAM) TO DDR2, the supporting speeds exchange to 533 Mbit/s. Controller is accessible in the form core, ready to embodiment in the microcircuits FPGA of economical families latticeECP2 and LatticeECP2M, and also family latticeSC Of extreme, optimized on the criterion of speed. Controller is calculated for the standard the memory DDR2 SDRAM and allows the possibility of programming latency.

As is known, the special feature of architecture latticeECP2 and LatticeECP2M is the presence of the high performance parallel interface of input-output, which supports the transfer of signals LVDS with speed to 840 Mbit/s. Resting on this possibility, the core of controller DDR2 SDRAM it can fulfill its functions, being synchronized on the pulses of clock frequency to 266 MHz, which is equivalent to the speed transmission data of 533 Mbit/s. On the assertion of company, this record speed for inexpensive FPGA. It goes without saying, are supported the lower speeds: 400, 333, 266, 200 and 133 Mbit/s.

Let us recall, during November of last year the company presented the realization of interface PCI express x1 and x4 for FPGA latticeSCM and LatticeECP2M.

latticeECP2 LatticeECP2M

LATTICEECP2 LATTICEECP2M